Outlier Patterns

Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up

This paper describes an example case study of $V_{min}$ debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. Two individual methods are proposed to prevent test patterns from capturing those responses.

September 2025 · Min-Hsin Liu, Ding-Wei Cheng, James Chien-Mo Li, Chris Nigh, Szu Huat Goh, Mason Chern, Bing-Han Hsieh, Subhadip Kundu
Main Flow of Adaptive Wafer Sort

ML-based Adaptive Wafer Sort to Preserve Diagnostic Information

This paper proposes machine learning based adaptive test method to reduce wafer sort test time while preserving test quality and diagnostic information.

July 2025 · Liu, Yun-Sheng, Liu, Min-Hsin, Li, James Chien-Mo